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AI Chip Design for High-Performance Computing

Cryogenic eDRAM-based Accelerator

Cryogenic eDRAM-based Accelerator

About Us

Our research focuses on high-performance hardware design for next-generation AI and advanced computing systems. We explore novel device, circuit, and architecture solutions to improve memory bandwidth, throughput, and energy efficiency in conventional computing platforms. Our research interests include:

  • Domain-Specific Accelerator Design (processing-in-memory accelerators based on SRAM, eDRAM, and emerging memory technologies)
  • Cryogenic CMOS Circuit Design (cryogenic memory and computing circuits)
  • VLSI System Design (FPGA-based accelerators and System-on-Chip design)

News

Current
We are looking for self-motivated students to work with us on AI accelerators and SoC chips.
02/2026
A paper entitled, "DSHD-CAM: High-Throughput RRAM CAM Leveraging Dynamic Shifted Hamming Distance for Genome Analysis" has been accepted in IEEE Transactions on Very Large Scale Integration Systems and is now available in IEEE Xplore.
12/2025
A paper entitled, "Design of An Aging-aware Memory with BTI-mitigated SA and System-Visible Lifetime Management" has been accepted in IEEE Transactions on Circuits and Systems I: Regular Papers and is now available in IEEE Xplore.
11/2025
A paper entitled, "ACIMC: A 342.7-TOPS/mm² eDRAM-based Analog Cryogenic In-Memory Computing Macro" has been accepted in IEEE Transactions on Circuits and Systems I: Regular Papers and is now available in IEEE Xplore.
09/2025
A paper entitled, "A Complementary 3T-Based eDRAM Macro for High-Density Dual-Direction CAM and Logic-in-Memory" has been accepted in IEEE Transactions on Circuits and Systems I: Regular Papers and is now available in IEEE Xplore.
09/2025
Wenkai Mo joined our research group as a Master's student. Welcome!
07/2025
A paper entitled, "A 5T0C eDRAM-Based Content Addressable Memory for High-Density Searching and Logic-in-Memory" has been accepted in IEEE Transactions on Very Large Scale Integration Systems and is now available in IEEE Xplore.
04/2025
A paper entitled, "HDD-RAM: A 40-nm 0.35V 25MHz Half-Select Disturb-Free Memory with Data-Aware 10T SRAM" has been published in Integrated Circuits and Systems and is now available in IEEE Xplore.
11/2024
A paper entitled, "Overview of Cryogenic CMOS Based Computing Systems" has been published in Integrated Circuits and Systems and is now available in IEEE Xplore.
05/2024
Our work on cryogenic in-memory computing accelerator has been accepted for publication at the IEEE Journal of Solid-State Circuits (JSSC) and is now available in IEEE Xplore 🎉
07/2023
Our work on SRAM-based in-memory computing BNN accelerator has been accepted for publication at IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I).
01/2023
Our work on cryogenic in-memory computing with multi-mode operations has been accepted for presentation at the IEEE Custom Integrated Circuits Conference (CICC) 2023.
01/2023
Our work on 4T gain-cell based cryogenic memory has been accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS) 2023.
01/2021
Our work on binarized CNN accelerator has been accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS) 2021 and has also been invited to the IEEE Transactions on Circuits and Systems II: Express Brief (TCAS-II) 🎉

Teaching

  • Graduate Courses:
    • VLSI Circuit and System Design
    • Advanced Digital Integrated Circuits Design (2024~2025, Spring)
  • Undergraduate Courses:
    • Digital Integrated Circuits Design
    • FPGA Design and Applications
    • Principle and Application of Microcomputer (2024~2025, Spring)